IEEE Trans Neural Netw
October 2012
Two ANNA neural-network chips are integrated on a 6U VME board, to serve as a high-speed platform for a wide variety of algorithms used in neural-network applications as well as in image analysis. The system can implement neural networks of variable sizes and architectures, but can also be used for filtering and feature extraction tasks that are based on convolutions. The board contains a controller implemented with field programmable gate arrays (FPGA's), memory, and bus interfaces, all designed to support the high compute power of the ANNA chips.
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October 2012
A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision.
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