Publications by authors named "Dominik Kleimaier"

Article Synopsis
  • The study introduces a dual-port cell design that helps eliminate pass disturbance in vertical NAND storage by using a special pass gate.
  • It highlights that the unique structure reduces the impact of electric fields during operation, allowing for a "disturb-free" state in NAND strings.
  • The design is compatible with current technology, allowing easy integration into smaller, advanced vertical NAND systems with minimal extra components.
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Article Synopsis
  • * A new approach using ferroelectric field-effect transistors (FeFETs) is proposed, allowing for dynamic reconfiguration without interrupting ongoing processes, effectively improving efficiency.
  • * Results demonstrate significant improvements, including a reduction in LUT and connection block area, power consumption savings, and considerable time savings for both context-switching and dynamic reconfiguration applications.
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Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage () state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high- state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low- state stability.

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Ferroelectric field-effect transistors (FeFETs) with a single gate structure and using the newly discovered ferroelectric hafnium oxide as an active material are attracting considerable interest for nonvolatile memory devices. However, such FeFETs struggle to achieve a large separation between the two logic states (memory window, MW) because of the thickness limitations of the ferroelectric film. Moreover, they are affected by detrimental disturbs coming from the read operation because of the shared write and read paths.

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