ACS Appl Mater Interfaces
March 2023
Steady progress in integrated circuit design has forced basic metrology to adopt silicon lattice parameter as a secondary realization of the SI meter that lacks convenient physical gauges for precise surface measurements at a nanoscale. To employ this fundamental shift in nanoscience and nanotechnology, we propose a set of self-organized silicon surface morphologies as a gauge for height measurements within the whole nanoscale (0.3-100 nm) range.
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