Publications by authors named "Dhafer J Almakhles"

This letter presents a new single-stage common ground type nine-level (9L) switched-capacitor inverter topology with single-phase operation. The primary objective of this topology is to reduce the leakage current, voltage boosting, and maintain the voltage across the switched capacitors. The output voltage (v) can be boosted up to two times the input voltage (v).

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The boost-switched capacitor inverter topology with reduced leakage current is highly suitable for distributed photovoltaic power generation with a transformerless structure. This paper presents a single-stage 5-level (5L) transformerless inverter with common ground (CG) topology for single-phase grid-connected photovoltaic application. A generalized version of the proposed topology is also presented.

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The focus of current research is to address the problem of robust output tracking, input delay compensation and disturbance attenuation performance for a family of stochastic systems by implementing the improved-equivalent-input-disturbance (IEID) estimator and the extended Smith predictor (ESP) technique. By integrating the observer and IEID-estimator together with ESP, a new closed-loop configuration is presented. Then, Lyapunov based mean-square asymptotic stability criterion is obtained.

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Developing of new photovoltaic inverter topologies is received more attention in the last few years. In particular, designing an active neutral-point-clamping inverter type structure is quite popular for PV applications. The output voltage is always half of the input voltage (v), which further increases the voltage rating of dc-link capacitors in the conventional three-level ANPC.

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Multilevel inverters play an important role in extracting the power from renewable energy resources and delivering the output voltage with high quality to the load. This paper proposes a new single-stage switched capacitor nine-level inverter, which comprises an improved T-type inverter, auxiliary switch, and switched cell unit. The proposed topology effectively reduces the DC-link capacitor voltage and exhibits superior performance over recently switched-capacitor inverter topologies in terms of the number of power components and blocking voltage of the switches.

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