The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter.

In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics.