Publications by authors named "Chiarulli D"

In this paper we present a novel methodology for classifying cells by using a combination of dielectrophoresis, image tracking and classification algorithms. We use dielectrophoresis to induce unique motion patterns in cells of interest. Motion is extracted via multi-target multiple-hypothesis tracking.

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Through five experiments, we demonstrate and characterize the basic functionality of imaging fiber bundles for optoelectronic chip-level interconnections. We demonstrate the transmission of spot arrays with spot sizes and a spot pitch roughly equal to 2 and 4 times the core pitch, respectively. We show that optoelectronic integrated circuits, including sources and detectors, can be butt coupled directly to fiber bundles without any additional optical elements.

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Chatoyant is a tool for the simulation and the analysis of heterogeneous free-space optoelectronic architectures. It is capable of modeling digital and analog electronic and optical signal propagation with mechanical tolerancing at the system level. We present models for a variety of optoelectronic devices and results that demonstrate the system's ability to predict the effects of various component parameters, such as detector geometry, and system parameters, such as alignment tolerances, on system-performance measures, such as the bit-error rate.

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We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors.

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While much effort has gone into developing efficient algorithms for calculating multipoint likelihoods, these calculations still form a significant bottleneck in the construction of genetic linkage maps. Our approach to this problem is based on incremental processing techniques, which attempt to reduce the time required to perform iterative computations by storing intermediate results during the initial iteration, so that they may be reused with little extra computation in subsequent iterations. We have developed an incremental program which provides a more efficient substitute for the CMAP program of the LINKAGE package.

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We have developed a version of the CRI-MAP computer program for genetic likelihood computations that runs the FLIPS and ALL functions of CRI-MAP in parallel on a distributed network of workstations. The performance of CRI-MAP-PVM was assessed in several linkage analyses using the FLIPS option of CRI-MAP on a map of 85 microsatellite markers for human chromosome 1. These analyses showed excellent speedup and efficiency and low distribution overhead.

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Hybrid optoelectronic computing structures are required for providing the information processing capabilities for the next generation of computing and communications systems. Reconfigurable optoelectronic interconnection networks are networks constructed of optical waveguides in which messages are switched or routed by means of optoelectronic devices. For these networks, the dichotomy between the bandwidth of the optical channels that carry messages and the performance of the electronic controllers and decoders that determine the routing and destination of those messages is a significant bottleneck.

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We present several optical interconnection structures which support communication requirements unique to multiprocessor systems, namely, broadcasting, multicasting, simulcasting, and multiport memory access. The structures are based on guided wave time division multiplexed channels and use coincident pulse techniques to optically demultiplex individual bits at selected destinations. We describe 1-and 2-D structures which are appropriate for processor to processor interconnections and for processor to memory interconnections, respectively.

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