Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes.