Publications by authors named "Chang-Woo Byun"

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing.

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In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application.

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In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance.

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It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In this work, a simple method has been introduced for formation of LDD structure in poly Si TFTs, Tilted Back Exposure (TBE) technique.

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In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to hot-electron trap at the drain junction.

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A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state.

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A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.

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The cross sections for single-electron photoionization in two-electron atoms show fluctuations which decrease in amplitude when approaching the double-ionization threshold. Based on semiclassical closed orbit theory, we show that the algebraic decay of the fluctuations can be characterized in terms of a threshold law sigma proportional to |E|(mu) as E --> 0(-) with exponent mu obtained as a combination of stability exponents of the triple-collision singularity. It differs from Wannier's exponent dominating double-ionization processes.

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