Mapping of integrated PIN diodes with a 3D architecture by scanning microwave impedance microscopy and dynamic spectroscopy.

This work addresses the need for a comprehensive methodology for nanoscale electrical testing dedicated to the analysis of both "front end of line" (FEOL) (doped semiconducting layers) and "back end of line" (BEOL) layers (metallization, trench dielectric, and isolation) of highly integrated microelectronic devices. Based on atomic force microscopy, an electromagnetically shielded and electrically conductive tip is used in scanning microwave impedance microscopy (sMIM). sMIM allows for the characterization of the local electrical properties through the analysis of the microwave impedance of the metal-insulator-semiconductor nanocapacitor (nano-MIS capacitor) that is formed by tip and sample.

Structural and Dielectric Properties of Subnanometric Laminates of Binary Oxides.

Capacitors with a dielectric material consisting of amorphous laminates of Al2O3 and TiO2 with subnanometer individual layer thicknesses can show strongly enhanced capacitance densities compared to the bulk or laminates with nanometer layer thickness. In this study, the structural and dielectric properties of such subnanometer laminates grown on silicon by state-of-the-art atomic layer deposition are investigated with varying electrode materials. The laminates show a dielectric constant reaching 95 combined with a dielectric loss (tan δ) of about 0.