12-Spin-Qubit Arrays Fabricated on a 300 mm Semiconductor Manufacturing Line.

Intel's efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes as well as production-level process control.

Ultra-High- Ferroelectric BaTiO Perovskite in the Gate Stack for Two-Dimensional WSe p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe transistor with a ferroelectric perovskite BaTiO gate oxide is presented. The 30 nm thick BaTiO gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe/BaTiO stack due to its high dielectric constant of 323.

Process integration and future outlook of 2D transistors.

The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the recent progress in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices based on stacked 2D TMD nanoribbons and specifically highlight issues that still need to be resolved by the 2D community in five crucial research areas: contacts, channel growth, gate oxide, variability, and doping. While 2D TMD transistors have great potential, more research is needed to understand the physical interactions of 2D materials at the atomic scale.