Highly-packed self-assembled graphene oxide film-integrated resistive random-access memory on a silicon substrate for neuromorphic application.

Resistive random-access memories (RRAMs) based on metal-oxide thin films have been studied extensively for application as synaptic devices in neuromorphic systems. The use of graphene oxide (GO) as a switching layer offers an exciting alternative to other materials such as metal-oxides. We present a newly developed RRAM device fabricated by implementing highly-packed GO layers on a highly doped Si wafer to yield a gradual modulation of the memory as a function of the number of input pulses.

Medium-Temperature-Oxidized GeO Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing.

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility.

Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization.

Gaseous pollutants, including nitrogen oxides, pose a severe threat to ecosystems and human health; therefore, developing reliable gas-sensing systems to detect them is becoming increasingly important. Among the various options, metal-oxide-based gas sensors have attracted attention due to their capability for real-time monitoring and large response. In particular, in the field of materials science, there has been extensive research into controlling the morphological properties of metal oxides.

Analytically and empirically consistent characterization of the resistive switching mechanism in a Ag conducting-bridge random-access memory device through a pseudo-liquid interpretation approach.

A new physical analysis of the filament formation in a Ag conducting-bridge random-access memory (CBRAM) device in consideration of the existence of inter-atomic attractions caused by metal bonding is suggested. The movement of Ag atoms inside the switching layer is characterized hydrodynamically using the Young-Laplace equation during set and reset operations. Both meridional and azimuthal curvatures of the Ag filament protruding from the Ag electrode are accurately calculated to track down the exact shape of the Ag filament with change in the applied voltage.

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO-based metal-ferroelectric-insulator-semiconductor stack.

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an AlOlayer between the SiOinsulator and the pure-HfOFE improves the read disturbance (2 = 2.

A novel physical unclonable function (PUF) using 16 × 16 pure-HfOferroelectric tunnel junction array for security applications.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits.

Effect of charge storage engineering on the NO gas sensing properties of a WO FET-type gas sensor with a horizontal floating-gate.

In this paper, we investigate the effects of charge storage engineering (CSE) on the NO gas sensing properties such as response, recovery, and sensitivity of a FET-type gas sensor with a horizontal floating-gate (FG) having tungsten trioxide (WO) as a sensing layer. When the FET transducer is set at an erase state (ΔV = -2 V), the holes injected into the FG by Fowler-Nordheim (F-N) tunneling increase the electron concentration at the WO-passivation layer interface. Accordingly, an oxidizing gas, NO, can take more electrons from WO, which increases the change in the FG voltage (ΔV) by a factor of 2.

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide.

For improving retention characteristics in the NOR flash array, aluminum oxide (AlO, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO/AlO/SiO, which take advantage of higher permittivity and higher bandgap of AlO compared to SiO and silicon nitride (SiN). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.

3-bit multilevel operation with accurate programming scheme in TiO/AlOmemristor crossbar array for quantized neuromorphic system.

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron.

Realization of Biomimetic Synaptic Functions in a One-Cell Organic Resistive Switching Device Using the Diffusive Parameter of Conductive Filaments.

Toward the successful development of artificial intelligence, artificial synapses based on resistive switching devices are essential ingredients to perform information processing in spiking neural networks. In neural processes, synaptic plasticity related to the history of neuron activity plays a critical role during learning. In resistive switching devices, it is barely possible to emulate both short-term plasticity and long-term plasticity due to the uncontrollable dynamics of the conductive filaments (CFs).

Proposition of deposition and bias conditions for optimal signal-to-noise-ratio in resistor- and FET-type gas sensors.

In the field of gas sensor studies, most researchers are focusing on improving the response of the sensors to detect a low concentration of gas. However, factors that make a large response, such as abundant or strong adsorption sites, also work as a source of noise, resulting in a trade-off between response and noise. Thus, the response alone cannot fully evaluate the performance of sensors, and the signal-to-noise-ratio (SNR) should additionally be considered to design gas sensors with optimal performance.

3D AND-Type Stacked Array for Neuromorphic Systems.

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation.

On-Chip Training Spiking Neural Networks Using Approximated Backpropagation With Analog Synaptic Devices.

Hardware-based spiking neural networks (SNNs) inspired by a biological nervous system are regarded as an innovative computing system with very low power consumption and massively parallel operation. To train SNNs with supervision, we propose an efficient on-chip training scheme approximating backpropagation algorithm suitable for hardware implementation. We show that the accuracy of the proposed scheme for SNNs is close to that of conventional artificial neural networks (ANNs) by using the stochastic characteristics of neurons.

Synaptic Characteristics of Amorphous Boron Nitride-Based Memristors on a Highly Doped Silicon Substrate for Neuromorphic Engineering.

In this study, the resistive switching and synaptic properties of a complementary metal-oxide semiconductor-compatible Ti/-BN/Si device are investigated for neuromorphic systems. A gradual change in resistance is observed in a positive SET operation in which Ti diffusion is involved in the conducting path. This operation is extremely suitable for synaptic devices in hardware-based neuromorphic systems.

A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area.

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions.

Pruning for Hardware-Based Deep Spiking Neural Networks Using Gated Schottky Diode as Synaptic Devices.

Deep learning represents state-of-the-art results in various machine learning tasks, but for applications that require real-time inference, the high computational cost of deep neural networks becomes a bottleneck for the efficiency. To overcome the high computational cost of deep neural networks, spiking neural networks (SNN) have been proposed. Herein, we propose a hardware implementation of the SNN with gated Schottky diodes as synaptic devices.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection.

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier.

Memristive and Synaptic Characteristics of Nitride-Based Heterostructures on Si Substrate.

Brain-inspired artificial synaptic devices and neurons have the potential for application in future neuromorphic computing as they consume low energy. In this study, the memristive switching characteristics of a nitride-based device with two amorphous layers (SiN/BN) is investigated. We demonstrate the coexistence of filamentary (abrupt) and interface (homogeneous) switching of Ni/SiN/BN/n-Si devices.

3D Integrable W/SiN/n-Si/p-Si 1D1R Unipolar Resistive Random Access Memory Synapse for Suppressing Reverse Leakage in Spiking Neural Network.

In this paper, we pose reverse leakage current issue which occurs when resistive random access memory (RRAM) is used as synapse for spiking neural networks (SNNs). To prevent this problem, 1 diode-1 RRAM (1D1R) synapse is suggested and simulated to examine their current rectifying chracteristics, Furthermore, high density of 1 K 3D 1D1R synapse array structure and its process flow are proposed.

Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks.

Spiking neural networks (SNNs) are considered as the third generation of artificial neural networks, having the potential to improve the energy efficiency of conventional computing systems. Although the firing rate of a spiking neuron is an approximation of rectified linear unit (ReLU) activation in an analog-valued neural network (ANN), there remain many challenges to be overcome owing to differences in operation between ANNs and SNNs. Unlike actual biological and biophysical processes, various hardware implementations of neurons and SNNs do not allow the membrane potential to fall below the resting potential-in other words, neurons must allow the sub-resting membrane potential.

I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High / Ratio.

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current ( ), 25% reduced subthreshold swing (), and 52% lower off-current ( ) than conventional Fin TFET through TCAD simulation results.

Implementation of Synaptic Device Using Various High- Gate Dielectric Stacks.

We investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based fieldeffect transistor (FET)-type memory device. An Al₂O₃/HfO₂/Si₃N₄/SiO₂ gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si₃N₄ and HfO₂ layers are designed to charge trap layer for synaptic device.