Publications by authors named "B Thorgrimsson"

Single electron spins bound to multi-phosphorus nuclear spin registers in silicon have demonstrated fast (0.8 ns) two-qubit gates and long spin relaxation times (~30 s). In these spin registers, when the donors are ionized, the nuclear spins remain weakly coupled to their environment, allowing exceptionally long coherence times.

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Phosphorus atoms in silicon offer a rich quantum computing platform where both nuclear and electron spins can be used to store and process quantum information. While individual control of electron and nuclear spins has been demonstrated, the interplay between them during qubit operations has been largely unexplored. This study investigates the use of exchange-based operation between donor bound electron spins to probe the local magnetic fields experienced by the qubits with exquisite precision at the atomic scale.

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State preparation and measurement of single-electron spin qubits typically rely on spin-to-charge conversion where a spin-dependent charge transition of the electron is detected by a coupled charge sensor. For high-fidelity, fast readout, this process requires that the qubit energy is much larger than the temperature of the system limiting the temperature range for measurements. Here, we demonstrate an initialization and measurement technique that involves voltage ramps rather than static voltages allowing us to achieve state-to-charge readout fidelities above 99% for qubit energies almost half that required by traditional methods.

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Semiconductor quantum dots containing more than one electron have found wide application in qubits, where they enable readout and enhance polarizability. However, coherent control in such dots has typically been restricted to only the lowest two levels, and such control in the strongly interacting regime has not been realized. Here we report quantum control of eight different transitions in a silicon-based quantum dot.

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We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied.

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