III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Electrical properties of GaSb/InAsSb core/shell nanowires.

Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2-3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al.

Single InAs/GaSb nanowire low-power CMOS inverter.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce.

Self-seeded, position-controlled InAs nanowire growth on Si: A growth parameter study.

In this work, the nucleation and growth of InAs nanowires on patterned SiO(2)/Si(111) substrates is studied. It is found that the nanowire yield is strongly dependent on the size of the etched holes in the SiO(2), where openings smaller than 180 nm lead to a substantial decrease in nucleation yield, while openings larger than ≈500nm promote nucleation of crystallites rather than nanowires. We propose that this is a result of indium particle formation prior to nanowire growth, where the size of the indium particles, under constant growth parameters, is strongly influenced by the size of the openings in the SiO(2) film.

High current density Esaki tunnel diodes based on GaSb-InAsSb heterostructure nanowires.

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.

Effects of crystal phase mixing on the electrical properties of InAs nanowires.

We report a systematic study of the relationship between crystal quality and electrical properties of InAs nanowires grown by MOVPE and MBE, with crystal structure varying from wurtzite to zinc blende. We find that mixtures of these phases can exhibit up to 2 orders of magnitude higher resistivity than single-phase nanowires, with a temperature-activated transport mechanism. However, it is also found that defects in the form of stacking faults and twin planes do not significantly affect the resistivity.

Growth mechanism of self-catalyzed group III-V nanowires.

Group III-V nanowires offer the exciting possibility of epitaxial growth on a wide variety of substrates, most importantly silicon. To ensure compatibility with Si technology, catalyst-free growth schemes are of particular relevance, to avoid impurities from the catalysts. While this type of growth is well-documented and some aspects are described, no detailed understanding of the nucleation and the growth mechanism has been developed.