Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors.

The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the -type organic-based CTM shows the widest threshold voltage shift (∆V ≈ 80 V), four distinct for a multi-bit memory operation and retained memory currents for 10 s with high memory on- and off-current ratio (I/I ≈ 5Ⅹ10).

Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure.

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO.

Solution-Processed Organic and Oxide Hybrid CMOS Inverter for Low Cost Electronic Circuits.

We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed - and -type semiconductor, InGaZnO solution and TIPS-pentacene/PMS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical - and -type transistor operations with low off-current.

Ferroelectric-Dielectric Mixed Buffer Layer for Enhanced Electrical Performance of Organic Ferroelectric Memory Transistors.

We suggest a facile method to reduce the surface roughness of the ferroelectric polymer insulator to enhance the electrical performance of the ferroelectric field effect memory transistors (FeFET). Ferroelectric-dielectric mixed buffer layer was used to reduce the high surface roughness of the single layer ferroelectric polymer insulator. The FeFET with mixed buffer bilayer (BL-FeFET) showed more than 25 times higher on-current (3.

Importance of Effective Surface Smoothness on the Electrical Performance of Organic Thin-Film Transistors.

We presented further analysis to explain how the surface morphology influence the mobility of the organic thin film transistors with gate insulator having large undulated surface (GU-OTFTs) and introduced a new parameter in order to clearly understand the relation between surface roughness and field-effect mobility. The average of the slope between two adjacent points on the surface of a gate insulator, or effective surface smoothness (ES), was closely investigated. A smooth-contact-pressing (SCP) process affected the surface smoothness of the P(VDF-TrFE) insulator with a significant change in root-mean-square roughness (Zrms).