Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories.

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase.

Random Telegraph Noise in 3D NAND Flash Memories.

In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models.

Learning of spatiotemporal patterns in a spiking neural network with resistive switching synapses.

The human brain is a complex integrated spatiotemporal system, where space (which neuron fires) and time (when a neuron fires) both carry information to be processed by cognitive functions. To parallel the energy efficiency and computing functionality of the brain, methodologies operating over both the space and time domains are thus essential. Implementing spatiotemporal functions within nanoscale devices capable of synaptic plasticity would contribute a significant step toward constructing a large-scale neuromorphic system that emulates the computing and energy performances of the human brain.

Silicon nanocrystal memories: a status update.

In the last decade, the silicon nanocrystal memory technology has received widespread interests from the scientific community working in the field of non-volatile solid-state memories, considering it as a feasible candidate for the post-Flash scenario. The immunity to stress-induced leakage current and the reduction of parasitic floating-gate capacitive couplings make the nanocrystal technology very attractive, especially when considering the CMOS compatible process flow. However, many open issues still exist for its development, first of all concerning its scaling perspectives.