Experimental investigation and digital compensation of DGD for 112 Gb/s PDM-QPSK clock recovery.

For asynchronous sampled systems such as Polarization Division Multiplexed Quadrature Phase Shift Keying, (PDM-QPSK), phase and frequency of the sampling clock is typically not synchronized to the data symbols. Therefore, timing adjustment, so called clock recovery and interpolation, must be performed in digital domain prior to signal demodulation in order to avoid cycle slips. For the first time, the impact of first order PMD, (DGD), is experimentally investigated and quantified for 112 Gb/s PDM-QPSK signal.